Term
| The following four main actions are common to all microprocessors. |
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Definition
| Fetch, decode, execute, and write |
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Term
| The CPU temporarily holds the data it is processing in this workspace. The size of the computer word (number of bits) that can be held in this location affects the computer’s power and speed. |
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| This microprocessor component handles arithmetic operations that include integers and logical Boolean operations. |
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| This internal component performs specialized math operations that involve numbers such as exponents and fractions. Modern CPUs include this component as part of their internal design; early CPUs required the purchase of a separate “math” coprocessor. |
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Term
| This type of number includes all positive and negative whole numbers. |
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Definition
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Term
| This type of number allows the position of the decimal place to move, allowing for the creation of a variety of numbers. |
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Term
| This component acts as the computer’s heartbeat. It sets a steady pace for all system activities. |
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Definition
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Term
Determine if the statement is true or false. If false, correct the statement.
The system bus runs at a higher clock frequency than the CPU. |
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Definition
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Term
| This special type of memory (SRAM) is a buffer used to store commonly-used instructions and data. Its inclusion in current processor designs is one reason why modern CPUs can achieve such high clock frequencies. |
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Definition
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Term
Correct the statement to make it true.
The backstreet bus is the high-speed channel dedicated to moving data between the external L2 cache and the CPU. |
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Definition
| The back side bus is the high-speed channel dedicated to moving data between the external L2 cache and the CPU. |
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Term
| This processor structure is configured as a sophisticated, data-processing assembly line within the chip. |
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Definition
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Term
| Processors can only go as fast as the (slowest / fastest) time each segment of the pipeline takes to fetch, decode, execute, and write an instruction. |
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Definition
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Term
| These instructions are part of the physical design of the processor. They are made up of logic gates. |
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Definition
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Term
| The CPU receives these two types of information via the system bus. |
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Definition
| Program code messages and user data |
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Term
| This type of chip design philosophy incorporates the use of many transistors and logic gates which hardwire instructions onto the chip itself. This provides a large “library” of instructions that can be accessed internally for processing. |
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Definition
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Term
Determine if the statement is true or false. If false, correct the statement.
Intel chips are designed to be backwards compatible with the instruction set that was introduced with the 8086 processor in 1978. This design is known as the x86 architecture. |
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Term
| This term describes the efforts made by chip designers and computer manufacturers to create new equipment and components that take advantage of modern technologies, yet still remain functional in older machines. |
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Definition
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Term
| This type of chip design philosophy advocates using a very limited set of internal instructions for processing, thereby reducing the number of on-die transistors and logic gates. This reduces chip size and manufacturing costs. |
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Definition
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Term
| This chip design philosophy introduced the pipeline concept. |
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Definition
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Term
Determine if the statement is true or false. If false, correct the statement.
Most modern processor designs merge both the CISC and RISC chip design philosophies. |
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Definition
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Term
| Intel’s Pentium 4 Northwood chip has a 20+ stage pipeline. The longer pipeline allows the processor to run at a (higher/lower) clock frequency. |
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Definition
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Term
| The Pentium 4 advanced dynamic execution unit acts as this, ensuring that each part of the pipeline assembly line has enough data to keep it from becoming idle. |
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Definition
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Term
| When the pipeline doesn’t have enough data to keep the chip busy, the branch prediction units begin anticipating what data the system will need next. This is the act of processing these predictions before they have actually been requested. |
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Definition
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Term
Circle the correct answer.
If the P4 makes an incorrect prediction and processes the wrong data, it wastes between 19 and 30 clock cycles. (High / low) clock frequencies help Intel processors compensate for the possibility of wrong guesses. |
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Definition
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Term
The Advanced Dynamic Execution Unit manages the efficient use of data in the pipeline. It is
primarily composed of three parts. These are the (1) which fetches instructions and makes predictions, the (2) which creates a map of all running progra |
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Definition
| (1) Branch target buffer, and (2) Translation look-aside buffer |
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Term
| The front end of the Pentium 4 chip is responsible for this. |
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Definition
| Controlling and managing the efficient routing of data into the pipelines. |
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Term
Determine if the statement is true or false.
In general terminology, a buffer is a temporary storage area for data or instructions. Buffers improve system efficiency by holding information until system resources are available to
process it. |
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Definition
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Term
| This term refers to the amount of time one component must wait to receive data from another component. |
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Definition
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Term
| After instructions pass through the Advanced Dynamic Execution Unit in the front end of the P4, they are sent from the allocator into four main scheduling queues. These queues direct information to the backend for processing by the Rapid Execution Engine. |
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Definition
Memory Scheduler
Fast ACU Scheduler
Slow Alu/General FPU
Simple FP Scheduler |
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Term
Determine if the statement is true or false. If false, correct the statement.
The rapid execution engine in the backend of the P4 is where instructions are executed after being sorted and scheduled for processing. |
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Definition
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Term
| The Pentium 4 Northwood has a ___________ consisting of two ALUs that run at twice the frequency of the processor. Doubling the speed of internal instruction processing is another one of the tactics used by Intel to compensate for the possibility of incor |
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Definition
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Term
Determine if the statement is true or false. If false, correct the statement.
a Pentium 4 hyper-threading technology allows a single processor to act logically as if it
were a dual processor system.
b The Windows XP operating system does not support |
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Definition
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Term
| This type of architecture uses multiple pipelines operating in parallel to process several instructions in the same clock cycle. This architecture is all hardware-based, thus specialized programs do not need to be written to take advantage of the technolo |
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Definition
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Term
Determine if the statement is true or false. If false, correct the statement.
a The AMD Athlon XP uses a 40-stage pipeline and more lines to compete with the Intel P4 20+ stage pipeline.
b Current AMD processors are a good value when comparing cost vs |
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Definition
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Term
| The G4 uses this specialized type of processing. |
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Definition
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Term
The G4 is able to process 128-bit instructions called Altivec instructions in its execution engine
known as the _____________ engine. |
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Definition
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Term
Intel P4: MMX, SSE, SSE2
AMD: 3D Now!
Apple: Altivec |
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Definition
| These are specialized instruction sets included on today’s generation of processors for optimizing graphics and video processing. |
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Term
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Definition
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Term
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Definition
| Reduced Instruction Set Computer |
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Definition
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Definition
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Definition
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Definition
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Definition
| Very long instruction word |
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Term
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Definition
| instructions executed per cycle |
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Term
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Definition
| Static Random Access Memory |
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Term
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Definition
| Millions of instructions per second |
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Term
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Definition
| Single instruction / multiple data |
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Term
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Definition
| Dynamic Random Access Memory |
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Term
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Definition
Branch target buffer
translation look aside buffer |
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