The Inverter (NOT circuit) performs the operation called 'inversion' or 'complementation.' The inverter changes one logic level to the opposite level. In terms of bits, it changes a 1 to a 0 and a 0 to a 1.

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A table showing the inputs and corresponding output
level of a logic circuit.

For the Inverter Truth Table Definition:

When a HIGH level is applied to an inverter input, a LOW level will appear on its output. When a LOW level is applied to its input, a HIGH will appear on its output. This operation is summarized in Table 3-1, which shows the output for each possible input in terms of levels and corresponding bits. A table such as this is called a 'truth table.'

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A graph of digital waveforms showing the proper time relationship of two or more waveforms and how each waveform changes in relation to the others.

A timing diagram is basically a graph that accurately displays the relationship of two or more waveforms with respect to teach other on a time basis. For example, the time relationship of the output pulse to the input.

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The complement of a variable is designated by a bar over the letter. A variable can take on a value of either 1 or 0. If a given variable is 1, its complement is 0 and vice versa.

The inverse or opposite of a number; in Boolean algebra, the inverse function, expressed with a bar over the bariable. The complement of a 1 is a 0, and vice versa.

The AND gate is one of the basic gates that can be combined to form any logic function. An AND gate can have two or more inputs and performs what is known as logical multiplication.

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Enable

(specifically, while using the AND gate)

To allow.

A common application of the AND gate is to enable (that is, to allow) the passage of a signal (pulse waveform) from one point to another at certain times and to inhibit (prevent) the passage at other times.

The OR gate is another of the basic gates from which all logic functions are constructed. an OR gate can have two or more inputs and performs what is known as logical addition.

An OR gate has two or more inputs and one output, as indicated by the standard logic symbols in Figure 3-17, where OR gates with two inputs are illustrated. An OR gate can have any number of inputs greater than one. Although both distinctive shape and rectangular outline symbols are shown, the distinctive shape OR gate symbol is used in this textbook.

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The NAND gate can be used as a universal gate; that is, NAND gates can be used in combination to perform the AND, OR, and inverter operations.

The term NAND is a contraction of NOT-AND and implies as AND function with a complemented (inverted) output. The standard logic symbol for a 2-input NAND gate and its equivalency to and AND gate followed by an inverter are shown in Figure 3-25(a), where the symbol ≡ means equivalent to.

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The NOR gate, like the NAND gate, is a useful logic element because it can also be used as a universal gate; that is, NOR gates can be used in combination to perform the AND, OR, and inverter operations.

The term NOR is a contraction of NOT-OR and implies an OR function with an inverted (complemented) output.

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Exclusive-OR and exclusive-NOR gates are formed by a combination of other gates. However, because of their fundamental importance in many applications, these gates are often treated as basic logic elements with their own unique symbols.

The output of an exclusive-OR gate is HIGH only when the two inputs are at opposite logic levels.

For an exclusive-OR gate, output X is HIGH when input A is LOW and input B is HIGH, or when input A is HIGH and input B is LOW; X is LOW when A and B are both HIGH or both LOW.

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Exclusive-OR and exclusive-NOR- gates are formed by a combination of other gates. However, because of their fundamental importance in many applications, these gates are often treated as basic logic elements with their own unique symbols.

Like the XOR gate, and XNOR has only two inputs. The bubble on the output of the XNOR symbol indicates that its output is opposite that of the XOR gate. When the two input logic levels are opposite, the output of the exclusive-NOR gate is LOW. the operation can be states as follows:

For an exclusive-NOR gate, output X is LOW when input A is LOW and input B is HIGH, or when A is HIGH and B is LOW; X is HIGH when A and B are both HIGH or both LOW.

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Most types of PLDs use some forms of AND array. Basically, this array consists of AND gates and a matrix of interconnections with programmable links at each cross point, as shown in fig 3-49. The purpose of the programmable links is to either make or break a connection between a row line and a column line in the interconnection matrix. For each input to an AND gate, only one programmable link is left intact in order to connect the desired variable to the gate input. Figure 3-49 illustrates an array after it has been programmed.

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Fuse Technology:

This was the original programmable link technology. It is still used in some SPLDs. The fuse is a metal link that connects a row and a column in the interconnection matrix. Before programming, there is a fused connection at each intersection. to program a device, the selected fuses are opened by passing a current through them sufficient to "blow" the fuse and break the connection. The intact fuses remain and provide a connection between the rows and columns. The fuse link is illustrated in Figure 3-51. Programmable logic devices that use fuse technology are one-time programmable (OTP).

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Antifuse technology:

An antifuse programmable link is the opposite of a fuse link. Instead of breaking the connection, a connection is made during programming. An antifuse starts out as an open circuit whereas the fuse starts out as a short circuit. Before programming, there are no connections between the rows and columns in the interconnection matrix. An antifuse is basically two conductors separated by an insulator. To program a device with antifuse technology, a programmer tool applies a sufficient voltage across selected antifuses to break down the insulation between the two conductive materials, causing hte insulator to become a low-resistance link. The antifuse link is illustrated in Figure 3-52. An antifuse device is also a one-time programmable (OTP) device.

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EPROM Technology:

In certain programmable logic devices, the programmable links are similar to the memory cells in EPROM (electrically programmable read-only memories). This type of PLD is programmed using a special tool known as a device programmer. The device is inserted into the programmer, which is connected to a computer running the programming software. Most EPROM-based PLDs are ont-time programmable (OTP). However, those with windowed packages can be erased with UV (ultraviolet) light and reprogrammed using a standard PLD programming fixture. EPROM process technology uses a special type of MOS transistor, known as a floating-gate transistor, as the programmable link. The floating-gate device utilizes a process called Fowler-Nordheim tunneling to place electrons in the floating-gate structure.

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EEPROM Technology:

'Electrically erasable programmable read-only memory technology' is similar to EPROM because it also uses a type of floating-gate transistor in E²CMOS cells. The difference is that EEPROM can be erased and reprogrammed electrically without the need for UV light or special fixtures. An E²CMOS device can be programmed after being installed on a printed circuit board, and many can be reprogrammed while operating in a system. This is called in-system programming (ISP). A flash array is a type of EEPROM array that not only can be erased much faster than with standard EEPROM technology but can also result in much higher density devices.

Many FPGAs and some CPLDs use a process technology similar to that used in SRAMs (static random-access memories). The basic concept of SRAM-based programmable logic arrays is illustrated in figure 3-54(a). A SRAM type memory cell is used to turn a transistor on or off to connect or disconnect rows and columns. For example, when the memory cell contains a 1 (green), the transistor is on and connects the associated row and column lines, as shown in part (b). When the memory cell contains a 0 (blue), the transistor is off so there is no connection between the lines, as shown in part (c).

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A PLD mounted on a programming fixture or development board into which a software logic design is to be downloaded; to programmable logic device that is being programmed.

A PLD to which a software logic design can be downloaded is called a target device.

The standard established by the Joint Test Action Group is the commonly used name for IEEE Std. 1149.1. The JTAG standard was developed to provide a simple method, called boundary scan, for testing programmable devices for functionality as well as testing circuit boards for bad connections--shorted pins, open pins, bad traces, and the like. More recently, JTAG has been used as a convenient way of configuring programmable devices in-system. As the demand of field-upgradable products increases, the use of JTAG as a convenient way of reprogramming CPLDs and FPGAs will continue to increase.

JTAG-compliant devices have internal dedicated hardware that interprets instructions and data provided by four dedicated signals. These signals are defined by the JTAG standard to be TDI (Test Data In), TDO (Test Data Out), TMS (Test Mode Select), and TCK (Test Clock). The dedicated JTAG hardware interprets instructions and data on the TDI and TMS signals, and drives data out on the TDO signal. The TCK signal is used to clock the process. A JTAG-compliant printed circuit board is represented in Figure 3-58.

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Complementary Metal-Oxide Semiconductor; a class of integrated logic circuits that is implemented with a type of field-effect transistor.

Two major digital integrated circuit (IC) technologies that are used to implement logic gates are CMOS and TTL. The logic operations of NOT, AND, OR, NAND, NOR, and exclusive-OR are the same regardless of the IC technology used; that is, an AND gate has the same logic function whether it is implemented with CMOS or TTL.

Transistor-transistor logic; a class of integrated logic circuit that uses bipolar junction transistors.

Two major digital integrated circuit (IC) technologies that are used to implement logic gates are CMOS and TTL. The logic operations of NOT, AND, OR, NAND, NOR, and exclusive-OR are the same regardless of the IC technology used; that is, an AND gate has the same logic function whether it is implemented with CMOS or TTL.

Propagation delay time, t_p, of a logic gate is the time interal between the application of an input pulse and the occurrence of hte resulting output pulse. There are two different measurements of propagation delay time associated with a logic gate that apply to all the types of basic gates:

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This parameter (t_p) is a result of the limitation on switching speed or frequency at which a logic circuit can operate. The terms 'low speed' and 'high speed,' applied to logic circuits, refer to the propagation delay time. The shorter the propagation delay, the higher the speed of the circuit and the higher the frequency at which it can operate.

Fan-out is specified in terms of unit loads. A unit load for a logic gate equals one input to a like circuit. For example, a unit load for a 74LS00 NAND gate equals one input to another logic gate in the 74LS series (not necessarily a NAND gate). Because the current from a LOW input (I_IL) of a 74LS00 gate is 0.4 mA and the current that a LOW output (I_OL) can accept is 8.0 mA, the number of unit loads that a 74LS00 gate can drive in the LOW state is

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