Term
|
Definition
A layer of memory that manages paging to the hard drive |
|
|
Term
|
Definition
The memory used to store currently rendering vertex buffers, textures, frambuffers, and render targets. |
|
|
Term
|
Definition
The comparison test for determing optimization improvment. |
|
|
Term
|
Definition
The comparison test for determing optimization improvment. |
|
|
Term
|
Definition
An application used to determing CPU performance. |
|
|
Term
|
Definition
Required for accurate call graph results |
|
|
Term
|
Definition
A collection type that counts time or events as your application runs |
|
|
Term
|
Definition
A collection type that tracks the measurements of hardware resources |
|
|
Term
|
Definition
a collection Type that shows parent child relationships |
|
|
Term
|
Definition
The guess the CPU makes to allow it to multi -process micro operations |
|
|
Term
|
Definition
An integer buffer that indexes single vertices in a vertex buffer |
|
|
Term
|
Definition
a buffer that contains information like XYZ or the normal of XYZ |
|
|
Term
|
Definition
|
|
Term
|
Definition
Small fast expensive hardware |
|
|
Term
|
Definition
The process by which we determine what not to process or render |
|
|
Term
|
Definition
The non=idle percentage of a given resource. |
|
|
Term
|
Definition
A group of code that runs more than 8% of total runtime. |
|
|
Term
|
Definition
a resource or stage in a pipeline that is the limiting factor in framerate |
|
|
Term
|
Definition
Moving processing from on over utilized resource to an under utilized resource. |
|
|
Term
|
Definition
Contains a minimum of 2 cores when you consider the CPU and GPU |
|
|
Term
|
Definition
The stage of the CPU where branch prediction and instruction fetching occurs. |
|
|
Term
|
Definition
The stage where the instruction pool operates out of order instructions |
|
|
Term
|
Definition
The stage where exceptions are thrown and brach prediction miss notification occurs |
|
|
Term
|
Definition
Another name for the Back-End stage and runs in order. This is where the CPU throws exceptions. |
|
|
Term
|
Definition
The stage where transform and lighting occurs |
|
|
Term
|
Definition
the bus that has slow download and fast upload. |
|
|
Term
|
Definition
the bus that has fast upload and fast download. |
|
|
Term
|
Definition
the number of bytes of modern cache lines. |
|
|